The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which the wiring line is connected to the semiconductor region, with a silicon film interposed.
The memory cell of DRAM (Dynamic Random Access Memory) is made up of a MISFET (Metal-Insulator-Semiconductor-Field Effect Transistor) for memory cell selection and a capacitor element for information storage connected in series to the other semiconductor (source or drain) region. To the other semiconductor (source or drain) region of the MISFET for memory cell selection is connected a data line, which is formed by an aluminum alloy film incorporated with silicon (Si). This silicon prevents the so-called alloy spiking which results from the connection between the semiconductor region (single crystal silicon) and the data line.
Two memory cells arranged at the position to which the data line is extended is constructed integrally with (or own in common) the other semiconductor regions of the individual MISFETs for memory cell selection. In other words, the area corresponding to the field insulation film to insulate and separate the other semiconductor region is eliminated, so that DRAM has a higher degree of integration.
The present inventors are developing a high-integrated DRAM in which the data line is connected to the other semiconductor region of the MISFET for memory cell selection through an intermediate conductive film. This intermediate conductive film is made of polycrystalline silicon film formed by the CVD process (Chemical Vapor Deposition) at the temperature about 630.degree.-650.degree. C. This polycrystalline silicon film is doped with an impurity such as phosphorus (P) and arsenic (As) for the reduction of its resistance.
One end of the intermediate conductive film is connected to the other semiconductor region, in the region defined by the side wall spacer formed on the side wall of the gate electrode of MISFET for memory cell selection, self-aligned to said gate electrode. The other end of the intermediate conductive film extends to the upper part of the gate electrode along the side wall spacer, with the gate electrode electrically separated. The data line is connected to the intermediate conductive film through the connecting hole formed in the first interlayer insulation film of the upper layer of the intermediate conductive film. On the top of the data line is formed the second interlayer insulation film. The first interlayer insulation film and second interlayer insulation film are made of silicon-based insulation film such as silicon oxide film and silicon nitride film.
The DRAM constructed as mentioned above has an advantage that the displacements of the mask for the other semiconductor region of MISFET for memory cell selection and the mask for the data line from the desired locations can be absorbed by the intermediate conductive film in the course of production. In other words, the intermediate conductive film permits the area of the other semiconductor region of MISFET for memory cell selection to be reduced in size as much as the amount of mask placement errors. This leads to an advantage that the area of memory cell can be reduced and hence the degree of integration for DRAM can be increased.
Also, the technology for connecting the wiring line to the semiconductor region, with a silicon film interposed, is described in, for example, Japanese Journal of Applied Physics, Vol. 18, p. 35-42, 1979.